Signal Integrity Project
Our project tackles one of the most stubborn pain-points in next-generation interconnect design: how to diagnose and mitigate connector-induced signal degradation at multi-hundred-gigabit data rates—without weeks of full-wave simulation.
We developed a 1D circuit express tool that captures modal impedance, loss, delay, and inter-pair coupling for every quasi-uniform slice of a connector/PCB assembly. The model scales naturally to mixed-mode analysis, so it predicts not only insertion and return loss but also mode conversion and crosstalk—all critical for PAM-4 links.
Measurement validation is performed in our lab to complete the signal integrity evaluation with validated simulation-to-measurement correlation in S-parameters and NRZ/PAM-4 eye diagrams.
Key Achievements
Loading resonance diagnosis and circuit transformation: Identified the root cause of loading resonances and interpreted 3D EM wave transmission/resonances in 1D circuit counterparts
Frequency headroom: Extended validated bandwidth from 40 GHz (2021) to 67 GHz (2024), adequate for 1.6 TbE and upcoming PCIe 7.0.
Speed: Reduced connector optimization loops from days to seconds, accelerating product cycles.
Awards: DesignCon 2024 Best Early-Career Paper Finalist, IEEE EPS Travel Award (ECTC 2025).
Products under anaysis: Genz, PCIe, OSFP, FPIO, MCIO, CPU Socket
Conferences and Publications
| Year | Venue & Paper | Key Contribution |
|---|---|---|
| 2023 | DesignCon – “Distributed-Physical-Based TL Model of PCIe 5.0 Connector for SI Fast Diagnosis” | First public dPBTL showing ≤ 2 % RMSE vs. FEM while delivering an order-of-magnitude speed-up. (ideals.illinois.edu) |
| 2024 | DesignCon – “m-TL Circuit Model of 5/6 G Connectors for Fast Resonance Crosstalk Analysis” | Extended dPBTL to multi-pair (m-TL) circuits, capturing inter-pair coupling with resonant ground cavity due to connector mating. (researchgate.net) |
| DesignCon – “Crosstalk Mechanisms of Ground Resonance and Stub on 5 G Connectors” | Quantified how differential signal transmission interacts with ground-cavity modes; provided design rules to avoid λ⁄2 resonances. (researchgate.net) | |
| IMS 2024 – “Integrated Distributed Equivalent Circuit Model of PCIe 5.0 Connector with AIC & Baseboard Loading Resonances for Fast SI Diagnosis” | Unified connector, housing and board effects into a single equivalent circuit; verified to 60 GHz, demonstrated on PCIe 5.0 connector mated on AIC and BB. (http://dx.doi.org/10.1109/IMS40175.2024.10600341) | |
| 2025 | IEEE T-MTT – “PCIe 5.0 Connector Distributed Physical-Based Circuit Model with Loading Resonances for Fast SI Diagnosis & Pathfinding” | Journal-length expansion of IMS with circuit-guided design pathfinding to enable PCIe 6.0 and PCIe 7.0 up to 128 GT/s PAM-4 (http://dx.doi.org/10.1109/TMTT.2024.3479132) |
| ECTC 2025 – “Mixed-Mode Distributed Physical-Based TL Model of 5 G Connectors for Fast SI Analysis on Ground Resonances & 112 Gbps PAM-4” | Extend dPBTL circuit tool to full mixed-mode domain. Identified the mixed-mode resonance mechanism with quantative EM analysis and circuit validation. Predicted mixed-mode S-parameter degradations and PAM-4 eye closure; validated at 112 Gbps. (http://dx.doi.org/10.1109/ECTC51687.2025.00118) | |
| ECTC 2025 – “Systematic Crosstalk Reduction Methods towards PCIe 7.0 PAM-4 on LoPro FPIO Connectors” | Introduced dielectric inserts & air-bridge grounds that meet the emerging 106 Gbps/lane spec with >10 dB crosstalk margin, demonstrated on FPIO. (http://dx.doi.org/10.1109/ECTC51687.2025.00287) | |
| IMS 2025 – “Mixed-Mode Distributed Physical-Based Model on OSFP Connector for Fast PAM-4 Channel Analysis up to 212.5 Gbps” | Applied mm-dPBTL to actual connector product (OSFP) with detailed quantative mixed-mode field diagnosis and circuit formulation. Desmonstrate accurate mixed-mode S-parameter prediction up to 60 GHz and channel analsysis up to 212.5 Gbps PAM-4 for 1.6 TbE link |
