Current Research

Transistor Laser (3-port Device)

Optoelectronic device research includes InGaP/GaAs lighting emitting transistors and transistor lasers, as well as light emitting transistors from other material systems. In addition to displaying unique electrical and optical properties, these devices allow novel three port operation utilizing both electrical and optical ports.

Advanced Transistor Device Design, Fabrication, and Modeling

Our group also works on the design, fabrication and modeling of high speed Heterojunction Bipolar Transistors (HBTs), using InP/GaAsSb double heterojuntion devices and pseudomorphic single heterojunction devices to obtain record setting high frequency operation. 

Cryogenic Vertical Cavity Surface Emitting Laser (Cryo-VCSEL)

(a) Schematic of the structure of the sub-micron aperture oxide VCSEL. The device structure is comparable to that of conventional VCSELs, with 0.9 μm oxide aperture. To achieve optimized RF performance, the VCSEL mesa is planarized using benzocyclobutene (BCB), ensuring improved uniformity and reduced parasitics. (b) The optical microscope top view of the fabricated Cryo-VCSEL device after dicing and packaging. (c) Infrared (IR) image of the sub-micron oxide aperture, showcasing the uniformity and precision of the aperture region critical for device functionality.

In addition to HBT and TL, our group also works on the design, fabrication and modeling of high-speed Cryo-VCSELs, which will be used in future high speed optical data interconnects in data centers and also supercomputers communications.

Mixed Signal/Microwave Circuit Design and Device Modeling

FIG. 3. VCSEL cross-sectional physical model with the corresponding equivalent circuit components. Rp and Cp are the parasitic pad resistance and capacitance. Rj and Cj are the total diode junction resistance and capacitance. Cox is the oxide capacitance. Cdiff and Cdep are the junction diffusion and depletion capacitance, respectively. Ls and Lg are the signal and ground inductance, respectively. Rs,p and Rs,n are the series resistance resulted from the p-DBR and n-DBR mirrors as well as the metal-semiconductor contact.

Our group’s modeling efforts focus on developing accurate small signal, large signal, and noise models to enable high speed circuit design using the most advanced devices.  We develop models and circuits for devices being fabricated by our HSIC processing group as well as for  international foundries, large corporations, and American defense contractors.

Signal Integrity

Our group’s SI team aims to develop a complementary fast express tool to reduce design turnaround time of high-speed interconnects for 5G/6G communication, 800 GbE/1.6 TbE/3.2 TbE system. We develop distributed physical-based transmission line (dPBTL) circuit system to fast predict and guide connector designs.